ASIC/FPGA Thought Papers |
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Verification of Skew and Jitter Tolerance
and Compensation in
High-Speed Interfaces |
Abstract
Historically, design engineers implementing high-speed interfaces have met numerous challenges in maintaining interface signal timing relationships and signal quality. Issues such as skew, jitter, crosstalk, and noise have been addressed through a combination of analog circuitry and board/chip physical design rules. Analog circuitry has been used for signal conditioning, filtering, impedance matching, and noise suppression, while physical design rules have targeted skew and crosstalk minimization.
In this paper we propose a common verification approach applicable to a variety of high-speed interfaces and based on reusable verification components that insert and monitor skew and jitter.
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Developing Pre-Silicon Prototypes of Embedded System-on-Chip
Designs - Aptix, Inc. |
Abstract
Engineers developing complex embedded System-on-Chip (SoC) designs are increasingly finding that traditional verification techniques are inadequate for delivering bug- free first-pass silicon. Hardware design problems made evident by complicated interactions among proprietary hardware, integrated third-party IP, low- level firmware, communication protocols, operating systems, and application software simply are not discovered by traditional simulator/testbench approaches. Companies that wait until test silicon is available before developing and integrating application software often find their market window closed when the product arrives. Many companies are turning to pre-silicon prototypes built from multiple FPGA devices as a technique for meeting these challenges. An approach to address these issues is presented.
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