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| Thought Paper |
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A Loosely Coupled C/Verilog Environment for System Level verification |
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| Abstract |
In this paper, we present a software C-Verilog interface, which is designed for the functional verification of any type of large system design. As a company specializing in ASIC verification, working with a wide range of systems including routers, parallel processors, and video applications, we not only developed this tool, but we are actively using it in large development environments with a variety of systems. In this paper, we will discuss some of the major concepts in this type of environment, along with the issues, and our experience with this tool in actual large development environments.
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