ASIC/FPGA Thought Papers |
| |
| Common Methodology for Complex Systems Verification: Case Studies |
Abstract
This DesignCon workshop presents a common verification methodology that has been applied to multiple complex system, SoC, and ASIC designs. This methodology provides predictable results, ensures re-use, minimizes project development risks, maximizes productivity of the verification, and enables easy scaling of the project. Verification environment features and implementation strategies are discussed and illustrated with numerous real-life examples.
|
|
 |
| |
| Design and Implementation of High-Speed Digital Equalizer |
Abstract
This Paper discusses challenges in designing and implementing an adaptive digital equalizer for high-speed modem applications and presents a design case study. It describes a methodology that provides a top-down design flow and a C-based verification approach, allowing a gradual transition from a Matlab simulation, used for algorithm development, to a bit-accurate C model, and, finally, to a synthesizable RTL. Results of the 3M gates FPGA chipset implementation are presented as well. The design and verification reusability, achieved through the methodology used in the project, is discussed in connection to a fully integrated ASIC implementation.
|
|
|
| |
Read more >
|
| |
< Back
|
