ASIC/FPGA Thought Papers |
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| Methodology and Code Reuse in the Verification of SOCs |
Abstract
Rapid developments in semiconductor technologies have opened a broad spectrum of opportunities for the electronics industry to produce complex systems from a number of pre-designed cores on a single chip. System-on-Chip (SoC) designs bring new verification challenges that become critical issues under the 'time-to-market' pressure. The reuse of verification code and methodology is a major factor providing significant reduction of the overall verification costs. A high-level description of the C-based verification system used for the verification and co-simulation of SoCs is described. In addition to this C language abstraction level, a set of pre-designed low-level C and VHDL routines create a powerful verification framework. The proposed verification methodology has proven to be reusable across a number of technologies and applications. The verification system's reusability is achieved by using a flexible user interface, environment structure, testbench design and verification methodology.
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| A Verification Methodology and Environment |
Abstract
This document lists the requirements for a next-generation verification environment, and describes characteristics of the environment that satisfy as many of the requirements as possible.
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