ASIC/FPGA Design |
| Verification Products |
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PREPT Verification Environment (Download datasheet)
Every project requires creating a new verification environment, which can take up to 12 weeks at the front-end of the product development cycle. At Patni, we understand that a standard, open language environment will provide you with predictable results, will shorten your product development schedule, and will allow your designers to reuse the environment, accelerating future product development cycles and saving you money. PREP is a rapidly deployable verification environment that defines standard techniques and methods for transactor development and test writing. It is an open and standards-based environment (C/C++) that uses pre-existing and third-party code.
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TestBenchPlus™ (Download datasheet)
TestBenchPlus is a transport layer for communicating test information
between C and Verilog/VHDL. It allows concurrent communication
and its API provides an easy-to-use interface for verification
and behavioral models.
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