Expertise |
We have a complete range of capabilities in this space that includes product definition, system & chip level architecture, ASIC/FPGA design & implementation, system & chip level verification and board design.
We have expertise with tools from various companies like Cadence, Mentor Graphics, Xilinx, Altera, Mathworks, Synopsys, TransEDA, Aldec, Magma, Teradyne, Agilent, Forte and others in the areas of: |
| |
| Computer Aided Engineering (CAE): Silicon Virtual Prototype, Timing Design, Intelligent Test Bench, Formal Analysis/Verification, Digital Simulation (VHDL/Verilog), Analog Simulation, Mixed Signal Simulation, Gate Level Simulation, Physical Effects Analysis, Synthesis, Analog Design, Gate Level Design, RTL Design, Design For Test, Hw/Sw Co-Verification, Acceleration & Emulation |
| |
| ESL (Electronic System Language): Hw/Sw/Co-Design, Design Entry, Analysis, Simulation/Verification, Synthesis |
| |
| CAD/CAM: PCB Development, MCM, Hybrid and Packaging, PCB CAM, Analysis (Timing, Signal Integrity, Electromagnetic Interference, Power, Metal Migration, Thermal), IC Simulation, DRC, Delay Calculators, Extractors, Silicon Manufacturing, Layout, Cell Libraries. |
| |
| Some Sample Projects |
 |
FPGA for PCI bus based controller card with backend logic support of Dual port RAM |
|
Complete Hardware Board Design for a Coin Dispenser Unit with multiple serial interfaces |
|
Design and Development of Handheld Mobile Devices based on RTOS |
|
Reference Hardware Design for Telematics Board to deployed on Automotive Vehicles |
|
Re-engineering of plug-able Interface cards into Graphic Visualization Terminals based on RTOS and supporting multiple Industrial Protocols |
|
Re-engineering of PCI bus based hardware cards to comply to new PCI Standards |
|
Design and Development of 3-Ch DMA with real-time DMA engine for MPC 855 on Xilinx |
|
Verification of 5M gate ASIC implementing multi-protocol processing functionality against specification using a test suite using specialized test |
|
Verification of a 24 board multi-site system with 14 different ASICs on each board for HW/SW verification including specification development, implementation and verification of 4M gate ASIC |
|
Design, implementation, and verification of a mixed-signal lower Power ASIC to address technology obsolescence |
|
IP Verification and bug-fixing of a multi-board system with complex ASICs implementing ATM and Ethernet connectivity. |
|
