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| Case Study |
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Low Power Mixed Signal ASIC Design |
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By engaging Patni's services from the concept to the design stage, a leading technology company created a
low power consumption chip in record time.
The Challenge
The customer's principal product line had been implemented using off the shelf
components. The client was informed that the primary device would be going
end-of-life shortly and they had to make a lifetime buy decision. This key
component had been designed by a sister division who by this time had been sold
off and thus the human and technical assets needed to do a re-design were no
longer available. After completion of a preliminary discovery period, it was agreed
the customer:
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Needed a replacement device with extremely low power consumption (2 microamps) |
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That such an power-constrained implementation would be difficult to attain in
any technology |
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Needed to quickly evaluate feasible options, select an appropriate technology
and initiate implementation |
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Had to call upon on a 3rd party partner that had both the technological, domain
expertise and bandwidth that could design, debug and deliver the chip in the
requisite (albeit, short) time. |
The Solution
Patni's experienced engineers examined the feasibility of the project by:
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Investigating alternate implementation technologies for power consumption and analog
capabilities |
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Submitting RFQs to Silicon vendors and obtain best pricing on qualifying technologies |
An appropriate Patni team was assembled to propose the complete solution including:
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Developing a detailed engineering plan and work breakdown schedule |
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Initiating and managing a 3rd party for Silicon place and route |
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Identifying and managing the Silicon vendor interface |
Implementation of the final design:
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Developed the design specification for single-chip implementation |
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Implemented the digital design in Verilog HDL |
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Synthesized the digital logic into a netlist |
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Integrated the digital design with the analog blocks |
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Created manufacturing test vectors |
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Secured sign off of the ASIC design with the silicon vendor |
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Assisted the customer in bringing up the device in the lab |
The Benefits
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The completed chip, running at the required performance was delivered on time |
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The chip actually required 5% less power than the
original design target |
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Accounting only for the direct expenses the total cost
to the customer was approximately 20% of what the
customer would have incurred had he attempted to do
the job in house. |
Patni Assets Deployed
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Project Management |
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ASIC Design & Verification |
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Mixed Signal Design |
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