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| Thought Paper |
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Block-Based Prototyping |
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| Abstract |
Engineers developing complex embedded System-on-Chip (SoC) designs are increasingly finding that traditional verification techniques are inadequate for delivering bug- free first-pass silicon. Hardware design problems made evident by complicated interactions among proprietary hardware, integrated third-party IP, low- level firmware, communication protocols, operating systems, and application software simply are not discovered by traditional simulator/testbench approaches. Further, companies that wait until test silicon is available before developing and integrating application software often find their market window closed when the product arrives. Many companies are turning to pre-silicon prototypes built from multiple FPGA devices as a technique for meeting these challenges.
Constructing a Pre-Silicon Prototype (PSP) of an SoC design using multiple FPGA's presents many challenges, including partitioning the monolithic design across the FPGA devices, working within the pin constraints of the FPGA's, mapping SoC constructs like gated clocks into struc tures more appropriate for FPGA's, and debugging with the PSP when bugs are uncovered in the design. Waiting until the final RTL is complete before beginning these tasks makes the total job considerably more difficult. A better approach is to follow a block-based prototyping methodology wherein design blocks are mapped to FPGA's and integrated with the rest of the design as the blocks become available.
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