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| Thought Paper |
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Verification of Skew and Jitter Tolerance and Compensation in High-Speed Interfaces |
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| Abstract |
Historically, design engineers implementing high-speed interfaces have met numerous challenges in maintaining interface signal timing relationships and signal quality. Issues such as skew, jitter, crosstalk, and noise have been addressed through a combination of analog circuitry and board/chip physical design rules. Analog circuitry has been used for signal conditioning, filtering, impedance matching, and noise suppression, while physical design rules have targeted skew and crosstalk minimization.
Hybrid parallel-serial interfaces that leverage high-speed serial links have evolved out of the need to scale bus bandwidth, while containing interface electrical and physical design challenges. The transition to serial and parallel-serial interfaces has been accompanied by an increase in design complexity caused by the loss of signal-to-signal timing relationships. The assumption that inter-signal timing relationships are fixed within functional simulations no longer holds. Using hybrid parallel-serial interfaces eliminates the notions of setup, hold, and fixed skew times at the interface, rendering static timing at the interface meaningless.
These factors call for a change in approach to functional verification that now must support uncertainty in edge placement, programmability of signal delay and skew over a wide range of values, variable timing relationships between channels, and the ability to vary timing parameters across and outside of the valid range.
In this paper, we propose a common verification approach applicable to a variety of high speed interfaces and based on reusable verification components that insert and monitor skew and jitter.
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